Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits

Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits
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Publisher :
Total Pages : 214
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ISBN-10 : OCLC:47212843
ISBN-13 :
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Book Synopsis Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits by : Kyung Tek Lee

Download or read book Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits written by Kyung Tek Lee and published by . This book was released on 1999 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt:


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