FPGA-based Digital Convolution for Wireless Applications

FPGA-based Digital Convolution for Wireless Applications
Author :
Publisher : Springer
Total Pages : 166
Release :
ISBN-10 : 9783319520001
ISBN-13 : 3319520008
Rating : 4/5 (01 Downloads)

Book Synopsis FPGA-based Digital Convolution for Wireless Applications by : Lei Guan

Download or read book FPGA-based Digital Convolution for Wireless Applications written by Lei Guan and published by Springer. This book was released on 2017-01-16 with total page 166 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear convolution in digital pre-distortion (DPD) enabled high-efficiency wireless RF transceivers; and fast linear convolution in massive multiple-input multiple-output (MIMO) systems. After reading this book, students and professionals will be able to: · Understand digital convolution with inside-out information: discover what convolution is, why it is important and how it works. · Enhance their FPGA design skills, i.e., enhance their FPGA-related prototyping capability with model-based hands-on examples. · Rapidly expand their digital signal processing (DSP) blocks: to examine how to rapidly and efficiently create (DSP) functional blocks on a programmable FPGA chip as a reusable intellectual property (IP) core. · Upgrade their expertise as both “thinkers” and “doers”: minimize/close the gap between mathematical equations and FPGA implementations for existing and emerging wireless applications.


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