Non-volatile Ferroelectric Transistor Based Memory Design

Download or read book Non-volatile Ferroelectric Transistor Based Memory Design written by Sandeep Thirumala and published by . This book was released on 2018 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Ferroelectric Field Effect Transistors (FEFETs) are emerging devices which have immense potential to replace conventional transistors due to their unique characteristics. They are realized by employing a ferroelectric in the gate stack of transistors with an optional metal layer in between the ferroelectric and dielectric. FEFETs can behave as volatile steep switching devices by virtue of their negative capacitance, beating the fundamental Boltzmann limit of 60mV/decade. On the other hand, with proper capacitance matching between the ferroelectric and the underlying transistor, FEFETs can also achieve non-volatile operation, by virtue of the retention of its polarization states in the absence of an external electric field.Gate leakage in FEFETs due to the presence of the floating intermediate metal layer plays a crucial role in determining the device-circuit operation. The effect of gate leakage in the context of steep switching FEFETs has been well understood. Similarly, there is a need to understand the impact of gate leakage in non-volatile FEFETs. This thesis extensively analyses the implications of gate leakage in non-volatile FEFETs and their memory designs. We show that the gate leakage shifts the device characteristics towards the left or right depending on the polarization stored in the ferroelectric. We observe that the robustness of long-term retention in non-volatile FEFETs enhances and becomes as high as that of standalone ferroelectric capacitor in the presence of gate leakage. We describe how distinguishability between the bi-stable polarization states can be lost in the presence of gate leakage. We propose work-function engineering in conjunction with a modified read operation to re-establish the lost distinguishability. We also showcase the implications of gate leakage on FEFET based 2T, 3T and 4T memory designs. We explain why the traditional operating bias conditions cannot be implemented in the presence of gate leakage. We use work-function engineering along with a new read scheme to overcome the drawbacks of gate leakage and achieve the desired functionality. FEFET memories with gate leakage showcase 33% increase in write time respect to memories neglecting gate leakage. At iso write time condition of 200ps, the write energy of FEFET memories with gate leakage increases by 43%. The read power of memories with gate leakage shows 4-6X increase compared to memories neglecting gate leakage. We showcase that the read-write metric overheads attained due to gate leakage can be significantly reduced by tuning device and circuit parameters.