Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport

Download or read book Simulation and Design of InAs Nanowire Transistors Using Ballistic Transport written by and published by . This book was released on 2007 with total page 109 pages. Available in PDF, EPUB and Kindle. Book excerpt: The purpose of this thesis is to describe the modeling of the performance of InAs nanowire MOSFETs and to study their performance as parameter of the transistor's structure (e.g., diameter, gate dielectric thickness, and gate dielectric constant) were changed. This study was performed using the FETToy (www.nanohub.org) modeling software [35, 36] developed at Purdue University. FETToy is composed of several Matlab scripts and is used to simulate ballistic transport in the calculation of the current-voltage (I-V) characteristics for nanoscale double gate silicon MOSFETs. By modifying the semiconductor's effective mass, the program can be used to model semiconductors other than silicon. This thesis presents in Chapter 2 the initial modeling results for an InAs nanowire MOSFET in comparison with the published experimental results for a 80 nm diameter nanowire MOSFET as reported by Bryllert et al.'s (Sweden) group [23, 24]. Comparisons were made of the simulation results to the experimental results for the transistor's drain current versus gate voltage to extract the threshold voltage, the transistor's output characteristics (drain current versus drain bias for various gate voltages), the log of the drain current versus the gate voltage (subthreshold plot), and the transconductance versus gate voltage for a drain voltage in the saturation region. Chapter 3 describes the results obtained from varying the transistor's structure from the initial one used in Chapter 2 to compare with the published experimental results. This includes the effects on transistor performance of variation in the nanowire diameter, gate dielectric thickness, and gate dielectric constant. This chapter also pursues the optimization of the device's performance by altering the device's structure. We conclude this thesis by summarizing the work presented here and offering suggestions for future work.